In the field of system design, lately, the reuse of past design modules becomes popular to enhance the design efficiency. The system scale is diverse, ranging from a system LSI which is a system comprised of a plurality of modules/blocks mounted on a single LSI, a PC board-level system comprising a plurality of LSIs arranged on a printed circuit board, to an equipment-level system constructed by arranging the PC boards to be interconnected in a housing.
In designing a system of any scale in a short period of time, it is practical to record parts of the system as intellectual property and reuse them in designing another system later.
Lately, in more cases, a designer reuses not only modules previously designed by the designer but also design modules protected as intellectual property by a third party. Sales and distribution of design modules protected as intellectual property by a third party becomes popular.
Owing to the reuse and distribution of design modules protected as intellectual property, the efficiency of system design is enhanced considerably. However, because the systems to be designed becomes larger each year, a verification process for ensuring the system operates properly becomes complex.
To verify a system design, including design modules protected as intellectual property by third parties, it is necessary to verify all modules constituting the system, which may be reviewed in two phases: verifying the internal operation of each module and verifying module-to-module connections.
For newly designed modules, verification must be performed in both two phases. However, for reused modules protected as intellectual property, which are used as part of the system design, its module internal operation does not need to be verified, but the module-to-module connections need to be verified to ensure the whole operation of the system runs smoothly.
Logic simulation is applied widely and commonly as a means for carrying out system design verification. The logic simulation is performed by furnishing test vectors for operation verification to a simulator for ensuring system operating as expected.
When carrying out the logic simulation of a system, data for simulating the operation of all modules constituting the system is necessary. To simulate the operation of the components, either design data itself or a verification model that is an abstract representation based on the design data is required. If design data is used, the design data can be verified, but it takes rather long processing time to execute the simulation sequentially due to the detailed descriptions of the design data. In contrast, the verification model enables verification in shorter processing time because of its abstract or simplified representation of internal operation of a module. However, the design data of a third party module cannot be 100% verified with a verification model because of its abstract or simplified nature.
Thus, taking the above-mentioned phases of verifying modules into consideration, the prior art system verification is commonly carried out to apply design data for newly designed modules and a verification model for reused modules protected as intellectual property among the modules constituting the system. In this widely used manner, the entire system can be verified rapidly, and designs including module-to-module connections can be verified.
In most cases, the verification model is provided by the developer of the provided modules by a third party who owns the intellectual property, with or without charge. In most cases, the verification model is distributed in a storage medium, such as CD-ROM or the like, onto which it has been written.
However, the use of the verification model presents the following problems. First, secret information leaks out by disclosing the verification model. Secondly, the verification model is subject to modification or alteration during specification change or debugging. Thirdly, it is difficult to quantitatively review how the verification model has actually been used. Fourthly, a fixed charge is set for use of the verification model, according to the currently applied charging method, and it is expensive.
With respect to the first problem, the verification model is normally disclosed in this way: all data required for logic simulation is written onto a storage medium to be distributed. Once the storage medium is distributed to a user, the user can examine and apply the verification model beyond its normal usage (for system verification). Generally, generating a verification model falls in another technical field than system design. In the above manner in which the medium having all data of the verification model is delivered, there is a risk of leaking out of the technique for generating the verification model.
With respect to the second problem, the verification model simulates the interface operation of a module in a system according to actual data. If bugs were carried in the verification model, the simulation may be different from the actual module operation. In addition, module specification change may cause discrepancy between the existing verification model and the actual module operation.
With respect to the third problem, the provider of the verification model is usually the provider of design modules protected as intellectual property and may wish to quantitatively review how the provided modules have been used and obtain data thereof for marketing purposes. In the foregoing manner in which the medium having all data of the verification model is distributed, the provider cannot know how the verification model users have used the verification model.
With respect to the fourth problem, the current charge for the verification model includes the price of the storage medium with the verification model data and the charge for maintenance service rendered to its users. However, the users must pay a fixed rate whether the user will use the verification model repeatedly or only once and the charge is generally high. In consequence, this would be a problem particularly for those users who want to apply the verification model to a small system to introduce a test module, which use lacks any economy of scale.